1. Field of the Invention
The present invention relates generally to methods for etching polysilicon layers within microelectronics fabrications. More particularly, the present invention relates to methods for globally etching polysilicon layers within microelectronics fabrications.
2. Description of the Related Art
As microelectronics fabrication device and structure dimensions have decreased and microelectronics substrate dimensions have increased, it has become increasingly more difficult to form through plasma etch methods within microelectronics fabrications patterned layers, such as patterned polysilicon layers, with uniform dimensions at various locations across a microelectronics substrate. Such patterned layers are even more difficult to form with uniform dimensions at various locations across a microelectronics substrate when such patterned layers are formed with multiple areal densities across the microelectronics substrate. Such dimensional non-uniformity of plasma etched patterned layers within microelectronics fabrications, including a plasma etched patterned polysilicon layer within a microelectronics fabrication, as a function of areal density of the patterned layer over a microelectronics substrate is commonly referred to as a micro-loading effect. A pair of schematic cross-sectional diagrams illustrating such a micro-loading effect is shown by FIG. 1 and FIG. 2.
Shown in FIG. 1 is a substrate 10 employed within a microelectronics fabrication. The substrate 10 has formed thereupon a blanket layer 12 which in turn has formed thereupon a series of patterned photoresist layers 14a, 14b, 14c, 14d and 14e, where the patterned photoresist layers 14a, 14b, 14c and 14d are formed into a high areal density region R1 over the substrate 10 while the patterned photoresist layer 14e is formed into a low areal density region R2 over the substrate 10. The series of patterned photoresist layers 14a, 14b, 14c, 14d and 14e is employed as a photoresist etch mask in forming a series of patterned layers from the blanket layer 12.
Referring now to FIG. 2, there is shown a schematic cross-sectional diagram illustrating the results of further processing of the substrate 10 whose schematic cross-sectional diagram is illustrated in FIG. 1. Shown in FIG. 2 is a schematic cross-sectional diagram of a microelectronics fabrication otherwise equivalent to the microelectronics fabrication whose schematic cross-sectional diagram is illustrated in FIG. 1, but wherein the blanket layer 12 has been etched within a plasma 16 while employing the patterned photoresist layers 14a, 14b, 14c, 14d and 14e as a photoresist etch mask layer. As is illustrated in FIG. 1, within the high areal density region R1 of the patterned photoresist layers the blanket layer 12 is under-etched in forming the incompletely etched patterned layer 12a, while in the low areal density region R2 of the patterned photoresist layers the patterned layer 12b is completely etched from the blanket layer 12, but there is sustained over-etch damage to the substrate 10 in the form of micro-trenches 18.
It is thus in general towards forming through plasma etch methods within microelectronics fabrications patterned layers with areal density variations while suppressing a micro-loading effect when forming those patterned layers within those microelectronics fabrications that the present invention is generally directed. Since it is quite common within microelectronics fabrications to form with substantial variations in areal density patterned polysilicon layers from blanket polysilicon layers within those microelectronics fabrications, it is more specifically towards forming through plasma etch methods within microelectronics fabrications patterned polysilicon layers with areal density variations while suppressing a micro-loading effect when forming those patterned polysilicon layers within those microelectronics fabrications that the present invention is more specifically directed.
With more particular regard to integrated circuit microelectronics fabrications, such plasma etch methods are commonly employed to form from blanket polysilicon layers patterned polysilicon layers with high areal density regions which form polysilicon gate electrodes and local interconnects associated with closely spaced field effect transistors (FETs), while simultaneously forming patterned polysilicon layers with low areal density regions forming global interconnects, such as bond pads.
Various novel plasma etch methods have been disclosed in the arts of microelectronics fabrication for forming patterned structures and patterned layers within microelectronics fabrications.
For example, Rossen, in U.S. Pat. No. 4,948,462 discloses a plasma etch method for forming from a blanket tungsten layer within an integrated circuit microelectronics fabrication a patterned tungsten layer within the integrated circuit microelectronics fabrication, where the patterned tungsten layer is formed while suppressing a lateral undercutting of the patterned tungsten layer beneath a patterned photoresist layer employed as a photoresist etch mask in forming the patterned tungsten layer. The plasma etch method employs an etchant gas composition comprising sulfur hexafluoride, nitrogen and chlorine.
In addition, Tamaki, in U.S. Pat. No. 5,254,213, discloses a reactive ion etch (RIE) plasma etch method for forming a contact window through a dielectric layer to access an underlying aluminum containing conductor layer within a microelectronics fabrication, where the contact window is etched through the dielectric layer while simultaneously suppressing sputtering of the aluminum containing conductor layer. The reactive ion etch (RIE) plasma etch method employs an etchant gas composition comprising sufficient nitrogen gas such that the aluminum containing conductor layer when exposed to the etchant gas composition is sufficiently nitrided such that its sputtering within the reactive ion etch (RIE) plasma etch method is suppressed.
Similarly, Rhoades et al., in U.S. Pat. No. 5,269,879, discloses a method for etching a silicon oxide, a silicon nitride or a silicon oxynitride dielectric layer in the presence of an aluminum, a titanium or a molybdenum containing conductor layer within an integrated circuit microelectronics fabrication, while avoiding sputtering of the conductor layer. The method employs a plasma simultaneously comprising sufficient fluorine containing species to etch the silicon oxide, the silicon nitride or the silicon oxynitride layer and sufficient nitrogen to suppress sputtering of the aluminum, the titanium or the molybdenum containing layer.
Finally, Wei et al., in U.S. Pat. No. 5,449,639, discloses a composite dry plasma etch/wet chemical etch method for forming from a blanket conductor metal layer within an integrated circuit microelectronics fabrication a patterned conductor metal layer within the integrated circuit microelectronics fabrication. The method employs a sacrificial anti-reflective coating (ARC) layer which attenuates reflections from the blanket conductor metal layer when forming the patterned conductor metal layer, while simultaneously serving as a removable layer which protects the patterned metal layer from wet chemical etchant induced corrosion.
Desirable in the art of microelectronics fabrication are additional plasma etch methods through which blanket polysilicon layers may be patterned to form patterned polysilicon layers within microelectronics fabrications, where the patterned polysilicon layers simultaneously have high areal density patterned polysilicon layer regions and low areal density patterned polysilicon layer regions, while suppressing a micro-loading effect when forming those patterned polysilicon layers. It is towards that goal that the present invention is directed.